1. Field of the Invention
Example embodiments of the present invention relate generally to a magnetic memory device and methods thereof, and more particularly to a magnetic memory device and methods of writing data into the magnetic memory device.
2. Description of the Related Art
Magnetic memory devices may include a magnetic tunneling junction (MTJ) cell having a tunneling layer as a storage node and magnetic layers disposed above and below the tunneling layer. Conventional magnetic memory devices may be nonvolatile memory devices which write bit data using a resistance characteristic of the MTJ cell.
The MTJ cell may have lower resistance if magnetization directions of magnetic layers of the MTJ cell are the same. In contrast, the MTJ cell may have higher resistance if magnetization directions of the magnetic layers not the same. If the MTJ cell is determined to have a lower resistance, the MJT cell may correspond to a first logic level (e.g., a higher logic level or logic “1”). If the MTJ cell is determined to have a higher resistance, the MJT cell may correspond to a second logic level (e.g., a lower logic level or logic “0”). Accordingly, bit data written into a conventional magnetic memory device may be read by measuring resistance or current of the MTJ cell and by comparing the resistance or current with a reference value.
FIG. 1 is a cross-sectional view illustrating a conventional magnetic memory device. Referring to FIG. 1, a gate electrode G may be disposed on a semiconductor substrate 10. Source and drain regions S and D may be respectively formed on the semiconductor substrate 10 between the gate electrode G and two field oxide layers (not shown) adjacent to the gate electrode G. The gate electrode G, and the source and drain regions S and D may collectively constitute a “field effect transistor” (hereinafter, referred to as a “transistor”). A digital line DL may be positioned at a given offset from the gate electrode G. A portion of a magnetic field used during a write operation of the conventional magnetic memory device (e.g., a random access memory (RAM) device) may be formed by the digit line DL. The digit line DL and the transistor may be covered with an interlevel dielectric (ILD) layer 12. A via hole h1 may be positioned in the ILD layer 12, and the via hole h1 may be filled with a conductive plug 14. A conductive pad 16 may also be positioned in the ILD layer 12. The conductive pad 16 may cover an upper surface of the conductive plug 14 and may extend up to the digit line DL by a given length. A MTJ cell 18 may be disposed on a given region of the conductive pad 16, such as on the digit line DL. An ILD layer 20 covering the conductive pad 16 and the MTJ cell 18 may further be positioned on the ILD layer 12. A via hole h2, through which an upper surface of the MTJ cell 18 is exposed, may be formed in the ILD layer 12. A bit line 22 filling the via hole h2 may further be positioned on the ILD layer 12.
FIG. 2 illustrates a flow of current in write and read operations of the conventional magnetic memory device of FIG. 1. In FIG. 2, a dotted line A1 may denote a current path in a write operation and a chain thin line A2 may denote a current path in a read operation.
Referring to FIG. 2, current may flow through a selected bit line BL during a write operation. Thus, even though a cell to be written is selected by a selected word line WL, a magnetic field generated by current that flows through the selected bit line BL may affect the selected MTJ cell 18 as well as an unselected (e.g., adjacent) MTJ cell (not shown) connected to the selected bit line BL. Accordingly, data scheduled to be written to a target cell may inadvertently be written to the unselected (e.g., adjacent) MTJ cell, thereby causing erroneous data to be stored in the conventional magnetic memory device, which may be referred to as having a “low selectively”.